1. Field of the Invention
The present invention is directed to an improved latch circuit for use with computing systems and, more particularly, an edge sensitive single clock latch with a skew compensated scan function.
2. Description of the Prior Art
The integrated circuits used in modern day computing systems include a plurality of latch circuits. The latch circuit is required to function in association with a scan capability. If a latch circuit possesses a scan capability, when the scan capability is utilized, the binary state of the latch circuit is read and recorded in a register along with the binary states of the other latch circuits. The contents of the register may then be read and displayed on a display screen for the purpose of comparing the binary states of the latch circuits with a set of correct binary states. In this fashion, erroneous data may be easily detected.
For example, referring to FIGS. 1a and 1b, a typical latch-scan arrangement is illustrated. In FIG. 1a, latch L2 is connected to the output of latch L1. Latch L3 is connected to the output of latch L2. Latch L4 is connected to the output of latch L3. Latch L5 is connected to the output of latch L4. Latch L6 is connected to the output of latch L5. Scan data is input to latch L1. A signal "A" energizes an input terminal of latches L1, L3, and L5. A signal "B" energizes an input terminal of latches L2, L4, and L6. The output of latch L6 is connected to an input of a register. The register is connected to a cathode-ray-tube (CRT) and associated circuitry for reading the contents of the register and displaying the register-contents on the CRT. FIG. 1b illustrates the voltage waveforms associated with signals A and B. In operation, referring to FIG. 1a in conjunction with FIG. 1b assume that a binary bit, representing the contents of latch L1, is stored within latch L1. In response to the first B signal pulse, the binary bit is moved to latch L2. In response to the first A signal pulse, the binary bit is moved to latch L3. In response to the second B signal pulse, the binary bit is moved to latch L4. In response to the second A signal pulse, the binary bit is moved to latch L5. In response to the third B signal pulse, the binary bit is moved to latch L6. In response to the third A signal pulse, the binary bit is moved to position "1" of the register. Other binary bits, representative of the contents of latches L2 through L6, have already been input to the register in a similar fashion. Therefore, the register is filled with binary bits representing the contents of latches L1 through L6. The register may be interrogated for its contents in order to study the binary bits thereby determining the operational condition of latches L1 through L6.
A typical prior art latch utilized for this purpose is the so-called polarity-hold level-sensitive-scan-design (LSSD) latch. The LSSD latch possesses the scan capability. However, this latch utilizes a multiple number of clocks to implement the scan capability. A multiple number of clocks is undesirable, from a designer's point of view, because each of these clock lines must be disposed on an integrated circuit chip. From the designer's point of view, it would be more desirable to utilize only one clock line.
Another type of latch which exists in the prior art is a so-called "D" type latch. The D-type latch is desirable, from a designer's point of view, because it is edge-sensitive to a clock pulse controlling the latch, that is, the binary state of the latch is changed in response to the leading edge of the clock pulse controlling the latch. Another desirable feature of the D-type latch is that it locks the data being input thereto at its present value prior to immediately transferring the locked data to an output latch. Therefore, the data cannot be changed in response to further changes in the input data state. Still another desirable feature of the D-type latch is that it utilizes only one clock to perform its function. However, a major disadvantage associated with the D-type latch is that it does not possess the above referenced scan capability. Therefore, the contents of the D-type latch cannot be checked and verified utilizing the scan feature.
Clocking is important in the functioning of a latch because it controls the latch function. However, when a multiple number of clocks are utilized to control the functioning of the latch, another problem is presented, that is, a so-called "skew" problem.
Clock skew is a problem when operating in the scan mode. In the scan mode, binary data from one latch, destined for storage in the register of FIG. 1a, must be stored in the next-sequentially disposed latch. However, the storage of this data is dependant upon the receipt of a clock pulse via a clock line. If a binary 1, for example, is ready for storage in the next-sequentially disposed latch, but the clock pulse is not received (due to various conditions associated with the clock pulse generator), the binary 1 will not be stored in the latch. When the clock pulse is received, the binary 1 may have been changed to a binary 0. In this case, a binary 0 will be stored in the next-sequentially disposed latch. Consequently, erroneous data is disposed within the register referenced above associated with the typical latch-scan arrangement of FIG. 1a.
The D-type latch has been modified to include the scan capabiltity associated with the LSSD type latch. However, the modified, reconstructed latch possessed a multiple number of clock lines, normally associated with the LSSD latch, needed to control its system functioning. This multiple number of clock lines is undesirable, from the designer's viewpoint, since it is difficult to implement this latch utilizing integrated circuit technology. Furthermore, unless the generation and the timing of the clock pulses, associated with the multiple number of clock lines, is carefully controlled, the clock skew problem is still present.